In order to incorporate more functions and to achieve better performance and less cost, integrated circuits are formed with increasingly smaller dimensions. In order to achieve smaller dimensions, circuits may be re-designed according to the design rules of the reduced scale. Accordingly, it can be ensured that not only the design with the smaller scale can be manufactured, but it can also be ensured that the circuit with the smaller scale can meet the design specifications.
It is, however, not cost effective to re-design the circuits for smaller dimensions. Since there are legacy circuits that have already been laid out with greater dimensions (scale), a cost-effective method has been explored to shrink the layouts of the legacy circuits, in which all the masks used for manufacturing the integrated circuits are shrunk by a same percentage. It is relatively easy to verify whether the shrunk circuits can be manufactured or not, for example, whether two neighboring features in the integrated circuits will be shorted or not if the integrated circuits are manufactured with the smaller scale. However, it is questionable whether the circuits, after they are shrunk, will be able to meet design specifications, for example, the timing requirement, the drive current requirement, or the like.
Conventionally, for shrinking a circuit, a target shrinking percentage is pre-determined, and then the feasibility of the shrinkage is determined. The feasibility includes whether the shrunk circuits can be manufactured or not, and whether the shrunk circuits can meet design specifications or not. If it is determined that the shrunk circuits cannot meet design specifications, foundries have to send the circuits back to clients for re-design, which, as aforementioned, will result in increased design cost. What is needed, therefore, is a method for overcoming the above-described shortcomings in the prior art.